Advisor: R. F. Davis, MSE.
The amorphous silica (a-SiO2) layer that electrically
insulates the poly-silicon gate from the silicon
substrate in a field effect transistor (FET) can
fail when a voltage is applied across it. This
event is called dielectric breakdown. In
traditional complementary metal-oxide semiconductor
(CMOS) applications dielectric breakdown is an
undesirable event in that it prevents further use
of the affected transistor. This breakdown
event is also used in the opposite sense, i.e.,
as a controllable means to produce non-volatile
memory (NVM). The latter technology is of
concern in the research currently being conducted
in the MSE Department at CMU. The technology
has not moved to a 90-nm process node wherein the
oxide layer thickness is approaching 1 nm. At
this size and below, it has been discovered that
the circuit models that could predict the breakdown
of a-SiO2 layers at larger dimensions were no longer
viable. This is currently causing significantly
increases in costs and time for technology redevelopment
of NVMs. Research in the MSE Department and
CMU is currently addressing the chemistry and physics
of the breakdown in these very thin oxide layers
via atomic resolution transmission electron microscopy
(TEM). In this program the REU student will
learn to use the high resolution TEM to investigate
the causes of breakdown in the oxide and to interpret
the results of his study in order to inform the
semiconductor community of the nature and causes
of the breakdown in these very thin oxides. The
student will also interface with students in Mechanical
Engineering who are conducting computer simulation
to develop dielectric breakdown models for the
oxide. As such, data and information will
be interchanged between both groups to arrive at
a complete understanding the science of the breakdown
process and a computer model that can be used to
predict breakdown in 90-nm and thinner oxides. |
